The technical field relates generally to non-volatile memory. More particularly, it pertains to enhancing row decoding for Flash memory devices.
Flash memory is a programmable, read-only, non-volatile memory similar to EPROM and electrically erasable programmable read-only memory (EEPROM). Flash memory differs from these other memory types in that erase operations are done in blocks.
Flash, EPROM, and EEPROM all must be erased before being written. When erasing EPROM, the entire chip is erased at once. EEPROM is automatically erased before a write on a byte basis. Flash is either erased in blocks (boot block or sectored erase block flash) or the entire chip at once (bulk erase flash).
Flash memory is composed of cells. Each cell is structured as a CMOS field effect transistor that incorporates a floating gate interposed between a control gate and the substrate of the transistor. The floating gate is isolated from the substrate by a thin oxide layer. An interpoly dielectric layer separates the floating gate from the control gate. The isolation of the floating gate from the substrate allows charges to be stored. This storage of charge is allows information to be stored and accessed whenever it is desired.
The charges are produced from two n-type diffusion regions formed from a silicon substrate. One of the n-type diffusion regions defines a drain and the other the source. These n-type diffusion regions are formed in the substrate of the cell. The substrate is a typical p-type layer formed from a silicon substance. When the cell is properly biased, an inversion layer forms in the p-type layer. The inversion layer allows the passage of charges. These charges can be used to store information on the floating gate of the cell.
The cells are arranged in rows and columns. To access a cell for reading, writing, or erasing, a particular row and a particular column are selected. A row of cells can be selected by presenting a row signal to a particular word line connected to the control gates of cells in the selected row. There may be multiple word lines to support multiple rows. A column of cells can be selected by presenting a column signal to a particular bit line connected to the drains of the cells in the selected column. There may be multiple bit lines to support multiple columns. When a particular word line and a particular bit line are selected, they identify a desired cell for access.
Due to manufacturing defects, a word line may undesirably short to a bit line. This will wreak havoc on the proper operation of a memory device. Multiple word lines are typically connected to a common voltage supply. Depending on the polarity of the common voltage supply, a large current may be drawn from the common voltage supply to flow through the word line, to the bit line that is shorted to the word line, to the drain of the cell that is connected to the bit line, and to the substrate of the cell when the junction formed from the interface of the drain and the substrate of the cell is forward biased. This large current may inhibit the common voltage supply to maintain its voltage level to support other word lines. This would render the memory device defective.
Thus, what is needed are devices and methods for enhancing row decoding so as to allow the short from the word line to the bit line to be repaired.
Devices and methods to support enhancing row decoding are discussed. An illustrative aspect includes a decoder for addressing a non-volatile memory device. The decoder includes a row decoder that receives input signals and outputs a decoded signal; a driver that receives the decoded signal to drive a word line; and a limiter that couples the word line to a negative supply. The limiter limits the current supplied to the word line by the negative supply so as to inhibit an undesired rate of flow of charge from the negative supply.
Another illustrative aspect includes a row decoder that receives input signals and outputs a decoded signal; a driver that receives the decoded signal to drive a node; a transfer mechanism to transfer a negative voltage to a word line; and a limiter that couples the word line to a negative supply.
Another illustrative aspect includes a method for decoding a non-volatile memory device. The method includes decoding a set of input signals to produce a row decoded signal; driving the row decoded signal so as to present a word line; and limiting a rate of flow of electric charge from the negative supply to the word line so as to inhibit an undesired rate of flow of electric charge from the negative supply to the word line.
Another illustrative aspect includes a method for decoding a non-volatile memory device. The method includes decoding a set of input signals to present a row decoded signal; driving a node by a driver that receives the decoded signal; transferring a negative supply to a word line by a transfer mechanism; and limiting a rate of flow of electric charge from the negative supply to the word line so as to inhibit an undesired rate of flow of electric charge from the negative supply to the word line.